The manufacture of integrated circuits (IC), semiconductor devices, flat panel displays, optoelectronics devices, data storage devices, magneto-electronic devices, magneto-optic devices, packaged devices, and the like entails the integration and sequencing of many unit processing steps. As an example, IC manufacturing typically includes a series of processing steps such as cleaning, surface preparation, deposition, lithography, patterning, etching, planarization, implantation, thermal annealing, and other related unit processing steps. The precise sequencing and integration of the unit processing steps enables the formation of functional devices meeting desired performance metrics such as speed, power consumption, and reliability.
As part of the discovery, optimization and qualification of each unit process, it is desirable to be able to i) test different materials, ii) test different processing conditions within each unit process module, iii) test different sequencing and integration of processing modules within an integrated processing tool, iv) test different sequencing of processing tools in executing different process sequence integration flows, and combinations thereof in the manufacture of devices such as integrated circuits. In particular, there is a need to be able to test i) more than one material, ii) more than one processing condition, iii) more than one sequence of processing conditions, iv) more than one process sequence integration flow, and combinations thereof, collectively known as “combinatorial process sequence integration”, on a single monolithic substrate without the need of consuming the equivalent number of monolithic substrates per material(s), processing condition(s), sequence(s) of processing conditions, sequence(s) of processes, and combinations thereof. This can greatly improve both the speed and reduce the costs associated with the discovery, implementation, optimization, and qualification of material(s), process(es), and process integration sequence(s) required for manufacturing.
Systems and methods for High Productivity Combinatorial (HPC) processing are described in U.S. Pat. No. 7,544,574 filed on Feb. 10, 2006, U.S. Pat. No. 7,824,935 filed on Jul. 2, 2008, U.S. Pat. No. 7,871,928 filed on May 4, 2009, U.S. Pat. No. 7,902,063 filed on Feb. 10, 2006, and U.S. Pat. No. 7,947,531 filed on Aug. 28, 2009 which are all herein incorporated by reference. Systems and methods for HPC processing are further described in U.S. patent application Ser. No. 11/352,077 filed on Feb. 10, 2006, claiming priority from Oct. 15, 2005, U.S. patent application Ser. No. 11/419,174 filed on May 18, 2006, claiming priority from Oct. 15, 2005, U.S. patent application Ser. No. 11/674,132 filed on Feb. 12, 2007, claiming priority from Oct. 15, 2005, and U.S. patent application Ser. No. 11/674,137 filed on Feb. 12, 2007, claiming priority from Oct. 15, 2005 which are all herein incorporated by reference.
Many of the unit processing steps comprise the formation or deposition of thin films of materials. Typical deposition techniques comprise atomic layer deposition (ALD), atomic vapor deposition (AVD), plasma enhanced atomic layer deposition (PE-ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma enhanced chemical vapor deposition (HDP-CVD), sub-atmospheric chemical vapor deposition (SACVD), ion assisted chemical vapor deposition (IA-CVD), and others. Most of these techniques use a showerhead arrangement to deliver the precursor gases to the surface of the substrate to deposit the thin film. The uniformity and properties of these materials are determined by the process parameters and details of the hardware used to deposit the thin films. Examples of process parameters comprise temperature, pressure, choice of gas species, gas flow rates, gas compositions, deposition time, applied plasma power (if used), etc. Examples of the details of the hardware (i.e. showerhead details) comprise the number of independent precursor channels in the showerhead, the spatial configuration of the channels, the number and size of the channels, the showerhead to substrate spacing, etc.
Typically, there are significant interactions between the process parameters, the details of the hardware, and the properties of the deposited material. A large number of experiments must be completed to optimize the process parameters to deposit a material with the desired properties. This number of experiments must be repeated for each hardware configuration. Showerhead assemblies are costly and have a long manufacturing time. Furthermore, they are designed to deposit material across the entire substrate. Therefore, a complete substrate must be used for each experimental process parameter test. In many cases, the substrate has undergone significant processing prior to the unit process being optimized. This further adds to the cost and complexity of the development activity.
Therefore, there is a need to develop showerhead assemblies that allow the cost efficient and timely optimization of the process parameters and hardware details to deposit materials with the desired properties. Furthermore, there is a need to develop showerhead assemblies that allow the interactions between the process parameters and the hardware details to be evaluated.